1. Field of the Invention
The present invention generally relates to an internal voltage generator of a semiconductor device, and more specifically, to an internal voltage generator which is able to obtain a stable internal voltage by monitoring oscillation of an internal voltage caused by noise or variation of load and optimizing characteristics of an internal voltage generating circuit.
2. Description of the Prior Art
FIG. 1 shows a conventional internal voltage generator 1, a conventional address circuit 2 and a conventional data output circuit 3. The internal voltage generator 1, the address circuit 2 and the data output circuit 3 are separated as an individual circuit in the conventional memory devices.
The internal generator 1 comprises a band gap reference generator 10, a VR1 generator 20, a VR2 generator 30, a VRC generator 40 and a Vcore driver 50, which are connected in series. The Vcore driver 50 outputs a final internal voltage Vcore. The address circuit 2 comprises an address pad 60 and an address decoder 61. The data output circuit 3 comprises a Dout buffer 70 and a DQ pad 71.
In a conventional semiconductor device, mask level processes should be repeated in order to reflect test results performed on a fabricated semiconductor device. As a result, time and cost are additionally required. Even when tests are performed in the package level, extra test pins other than conventional address input pins or data output pins are required.